1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to an electrostatic discharge protection device suitable to protect a circuit of the semiconductor device from electrostatic discharge.
2. Background of the Related Art
Recently, as chip size becomes smaller, the size of an electrostatic discharge protection device also becomes smaller. However, with the advent of the highly integrated or high speed circuit, the capacity of static electricity generated around a junction of the electrostatic discharge protection circuit becomes a primary cause of RC delay.
When using a related art parasitic bipolar transistor as the electrostatic discharge protection circuit there is a limitation for maintaining protection from the static electricity while simultaneously reducing the junction static electricity capacity. In general, a field transistor is used for the related art parasitic bipolar transistor. However, a thyristor can discharge currents over two times greater than the bipolar transistor. Thus, a more efficient small junction area electrostatic discharge protection circuit is realized with the thyristor relative to the bipolar transistor.
In order to overcome the limitation, a method using the thyristor such as a Silicon Controlled Rectifier (SCR) was introduced in the U.S. patent application Ser. No. 4,896,243. This related art electrostatic discharge protection device uses the inner pressure of the well. As illustrated in FIG. 1, an N well 2 is formed on a first predetermined area of a P type substrate 1. The N well 2 is injected with a low density impurity material. In the N well 2, a high density first N.sup.+ impurity region 3 and a first P.sup.+ impurity region 4 are formed. On a second predetermined area of the P type substrate 1 outside the N well 2, a high density second N.sup.+ impurity region 3a and a second P.sup.+ impurity region 4a are formed. The electrostatic discharge protection circuit is illustrated in the form of an equivalent circuit in FIG. 2. The N well 2 of FIG. 1 corresponds to a first N layer 22. The first P.sup.+ impurity region 4 of FIG. 1 is formed by impurity diffusion and corresponds to a first P layer 24 of FIG. 2. Accordingly, a PN junction is made by the first N layer 22 and the first P layer 24. The first P layer 24 is also connected to a pad (PAD). The second N.sup.+ impurity region 3a of FIG. 1 corresponds to a second N layer 23 of FIG. 2, and thus, a PN junction is formed with the P type substrate 1 of FIG. 1. The second N.sup.+ impurity region 3a and the second P.sup.+ impurity region 4a are connected to a ground terminal or Vss.
In this electrostatic discharge protection device, if static electricity is applied as illustrated in FIG. 1, a breakdown occurs in the N well 2, and a carrier is injected to the P type substrate 1. The injected carrier goes into the junction of the P type substrate 1 and the second N.sup.+ impurity region 3a to thereby operate an NPN bipolar transistor. At last, a PNPN path forms there so that the carriers applied are discharged due to the static electricity.
However, in the case where the silicon controlled rectifier uses the inner pressure of the well, because the trigger voltage is a high voltage of about 30-50 V, the gate insulating layer or the junction of the inner circuit may be broken before the electrostatic discharge protection element.
Accordingly, to lower the trigger voltage of the silicon controlled rectifier, another related art method uses the junction's inner pressure, not the well's inner pressure. As illustrated in FIG. 3, in the electrostatic discharge protection device using the junction's inner pressure, the inner pressure is about 10-15 V. However, when the thickness of the gate insulating layer is below 100 .ANG., the breakdown voltage of the gate insulating layer is about 12 V so that the junction's inner pressure and the gate insulating layer's breakdown voltage are almost the same. Accordingly, the characteristics of the gate insulating layer are decreased because of the static electricity. Further, this problem increases in the highly integrated circuits above 256 DRAM because the gate insulating layer is thinner.
To solve the gate insulating layer breakdown problem, a thyristor is used as the electrostatic discharge protection device and an additional trigger circuit can be formed. The additional trigger circuit generates a hot carrier when the static electricity is applied to lower the trigger voltage of the thyristor. The operation of a related art electrostatic discharge protection device using the thyristor and the hot carrier generating circuit is illustrated in FIG. 4. An earlier form of electrostatic discharge protection circuit for reinforcing the positive polarity (+) of Vcc with respect to Vss is an SCR made up with the bipolar transistors Q1 and Q2 using NPN and PNP. N-well and P-well resistances are respectively resistors R.sub.NW and R.sub.PW as illustrated in FIG. 4. The SCR is triggered in a low impedance state by the plate current that has a hot carrier injected from NMOS transistor M1 connected to the base of the Q1. Transistors M2-M5 control the trigger of the SCR according to the variation of the trigger variation M1, and allow the generation of the hot carrier only during the generation of electrostatic discharge (ESD). The transistor M2 coupled with the gate of M1 supplys Vcc power and thus is connected as the capacitor. The gate of the transistor M1 is discharged as Vss by the turn-on of the transistor M3 according to the turn-on of the transistor M5. The geometrical structure of the transistors M2 and M3 is used for guaranteeing a gate voltage Vgate larger than the voltage of the NMOS FET during the generation of ESD. In the operation of the electrostatic discharge protection circuit using the hot carrier generation circuit, the transistor M3 prevents the trigger of SCR and forms the gate voltage Vgate of M1 according to the Vss. Further, transistor M4 is used as the ESD clamp to limit the voltage crossing the gate oxide layer of M2.
However, these related art electrostatic discharge protection methods using the hot carrier still have various disadvantages.
First, as the device operates at a high speed when using the inner pressure of the junction, the gate insulating layer gets thinner. Accordingly, the insulating layer's inner pressure is lowered. However, the junction's inner pressure is not lowered. Therefore, the static electricity cannot be prevented using the junction's inner pressure.
Second, when using the hot carrier, if the static electricity is accumulated by the degradation of the circuit itself because of the hot carrier generation, the trigger circuit does not operate exactly.
Third, the additional circuit that generates the hot carrier complicates the structure and increases costs.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.